54 #ifndef AVCODEC_MIPS_LSP_MIPS_H
55 #define AVCODEC_MIPS_LSP_MIPS_H
57 #if HAVE_MIPSFPU && HAVE_INLINE_ASM
58 #if !HAVE_MIPS32R6 && !HAVE_MIPS64R6
61 static av_always_inline void ff_lsp2polyf_mips(
const double *lsp,
double *
f,
int lp_half_order)
71 for(
i=2;
i<=lp_half_order;
i++)
73 double tmp, f_j_2, f_j_1, f_j;
74 double val = lsp[2*
i];
77 "move %[p_f], %[p_fi] \n\t"
78 "add.d %[val], %[val], %[val] \n\t"
80 "ldc1 %[f_j_1], 0(%[p_f]) \n\t"
81 "ldc1 %[f_j], 8(%[p_f]) \n\t"
82 "neg.d %[val], %[val] \n\t"
83 "add.d %[tmp], %[f_j_1], %[f_j_1] \n\t"
84 "madd.d %[tmp], %[tmp], %[f_j], %[val] \n\t"
85 "addiu %[j], %[i], -2 \n\t"
86 "ldc1 %[f_j_2], -8(%[p_f]) \n\t"
87 "sdc1 %[tmp], 16(%[p_f]) \n\t"
88 "beqz %[j], ff_lsp2polyf_lp_j_end%= \n\t"
89 "ff_lsp2polyf_lp_j%=: \n\t"
90 "add.d %[tmp], %[f_j], %[f_j_2] \n\t"
91 "madd.d %[tmp], %[tmp], %[f_j_1], %[val] \n\t"
92 "mov.d %[f_j], %[f_j_1] \n\t"
94 "mov.d %[f_j_1], %[f_j_2] \n\t"
95 "ldc1 %[f_j_2], -16(%[p_f]) \n\t"
96 "sdc1 %[tmp], 8(%[p_f]) \n\t"
98 "bgtz %[j], ff_lsp2polyf_lp_j%= \n\t"
99 "ff_lsp2polyf_lp_j_end%=: \n\t"
101 : [f_j_2]
"=&f"(f_j_2), [f_j_1]
"=&f"(f_j_1), [
val]
"+f"(
val),
102 [
tmp]
"=&f"(
tmp), [f_j]
"=&f"(f_j), [p_f]
"+r"(p_f),
103 [j]
"+r"(j), [p_fi]
"+r"(p_fi)
110 #define ff_lsp2polyf ff_lsp2polyf_mips
static double val(void *priv, double ch)
MIPS assembly defines from sys/asm.h but rewritten for use with C inline assembly (rather than from w...
__asm__(".macro parse_r var r\n\t" "\\var = -1\n\t" _IFC_REG(0) _IFC_REG(1) _IFC_REG(2) _IFC_REG(3) _IFC_REG(4) _IFC_REG(5) _IFC_REG(6) _IFC_REG(7) _IFC_REG(8) _IFC_REG(9) _IFC_REG(10) _IFC_REG(11) _IFC_REG(12) _IFC_REG(13) _IFC_REG(14) _IFC_REG(15) _IFC_REG(16) _IFC_REG(17) _IFC_REG(18) _IFC_REG(19) _IFC_REG(20) _IFC_REG(21) _IFC_REG(22) _IFC_REG(23) _IFC_REG(24) _IFC_REG(25) _IFC_REG(26) _IFC_REG(27) _IFC_REG(28) _IFC_REG(29) _IFC_REG(30) _IFC_REG(31) ".iflt \\var\n\t" ".error \"Unable to parse register name \\r\"\n\t" ".endif\n\t" ".endm")